4031 64-bit serial-in serial-out shift register. S selects between D (when 0) and E serial inputs. Y is Q delayed by half a cycle (i.e. clocked on falling edge). +----------+ E |1 +--+ 16| VCC CLK |2 15| D |3 14| |4 13| Y |5 4031 12| Q |6 11| /Q |7 10| S GND |8 9| CLKout +----------+ [This information is part of the GIICM]