Date: 19990304 From: Uwe Zimmermann Organization: Royal Institute of Technology, Stockholm, Sweden To: Jaap van Ganswijk Subject: chip question ... Hej Jaap, Here are some additions: The pinout of the PLX_technology PCI interface chip PLX9050: ---------------------------------------------- 9050,PCI target interface chip,PLX_technology,PQFP160,160,Vdd,AD23,AD22,AD21,AD19,Ad18,AD17,Vss,Vdd,AD16,C/BE2#,FRAME#,IRDY#,TRDY#,DEVSEL#,STOP#,LOCK#,PERR#,SERR#,PAR,C/BE1#,AD15,AD14,AD13,Vss,Vdd,AD12,AD11,AD10,AD09,AD08,CBE0#,AD07,AD06,AD05,AD04,AD03,AD02,Vss,Vdd,Ad01,AD00,INTA#,NC,LBE3#,LBE2#,LBE1#,LBE0#,Vdd,Vss,LAD31,LAD30,LAD29,LAD28,LAD27,LAD26,LAD25,LAD24,LAD23LAD22,LAD21,BCLKo,ALE,Vss,Vdd,NC,MODE,LAD20,LAD19,LAD18,LAD17,LAD16,LAD15,LAD14,LAD13,LAD12,LAD11,LAD10,Vss,Vdd,LAD09,LAD08,LAD07,LAD06,LAD05,LAD04,LAD03,LAD02,LAD01,LAD00,LA02,LA03,LA04,LA05,LA06,LA07,LA08,TEST,LA09,LA10,LA11,Vdd,Vss,LA12,LA13,LA14,LA15,LA16,LA17,LA18,LA19,LA20,LA21,LA22,LA23,LA24,LA25,LA26,Vss,Vdd,LA27,ADS#,BLAST#,WR#,RD#,LW/R#,LRDY#,BTERM#,CS0#,CS1#,LRESET#,LHOLDA,LHOLD,LCLK,LINTi2,LINTi1,USER0/Wait0#,USER1/LLOCKo#,USER2/CS2#,USER3/CS3#,EECS,EED0,EESK,EEDI,Vdd,Vss,RST#,CLK,AD31,AD30,AD29,AD28,AD27,AD26,AD25,AD24,C/BE3#,IDSEL,Vss ---------------------------------------------- Yours, Uwe. -------------- Uwe Zimmermann Dipl. Phys. Department of Electronics Solid State Electronics Royal Institute of Technology Electrum 229 S-16440 Kista-Stockholm Sweden http://www.ele.kth.se/FTE/personal/pers_uwe.html ------------------------------------------------