74305 8-line inverting/noninverting divide by 2 clock driver. Four outputs in phase with CLK, four out of phase. +----------+ Q3 |1 +--+ 16| Q2 Q4 |2 15| Q1 GND |3 14| /RST GND |4 74 13| VCC GND |5 305 12| VCC /Q5 |6 11| CLK /Q6 |7 10| /PRE /Q7 |8 9| /Q8 +----------+ [This information is part of the GIICM]