*68681 *dual asynchronous receiver/transmitter (duart) *Philips, orig from Motorola? *19900122/wjvg 0 rw mode register a (mr1a,mr2a) rw 1....... yes/no rxrts control rw .1...... ffull/rxrdy rxint select rw ..1..... block/char error mode/char rw ...00... with parity rw ...01... force parity rw ...10... no parity rw ...11... multi-drop parity mode rw .....1.. odd/even parity rw ......nn bits per character-5 (5,6,7,8) after reading or writing once: (reset in cra) rw 00...... normal channel mode rw 01...... auto echo rw 10...... local loop rw 11...... remote loop rw ..1..... yes/no txrts control rw ...1.... yes/no txcts enable rw ....knnn stop bit length is k+0.5+nnn/16+0.5*(!k && 5 bits/char) 1 w clock select register a (csra) with clock = 3.6864 MHz w rrrr.... receiver clock select w ....wwww transmitter clock select acr[7]=0 acr[7]=1 w 0000 50 75 w 0001 110 110 w 0010 134.5 134.5 w 0011 200 150 w 0100 300 300 w 0101 600 600 w 0110 1200 1200 w 0111 1050 ? 2000 w 1000 2400 2400 w 1001 4800 4800 w 1010 7200 1800 w 1011 9600 9600 w 1100 38400 19200 w 1101 timer timer w 1110 ip4-16x ip4-16x for receiver clock select w 1111 ip4-1x ip4-1x for receiver clock select w 1110 ip3-16x ip3-16x for transmitter clock select w 1111 ip3-1x ip3-1x for transmitter clock select 1 r sra status register a (sra) r 1....... received break (from top of fifo) r .1...... framing error (from top of fifo) r ..1..... parity error (from top of fifo) r ...1.... overrun error r ....1... txemt r .....1.. txrdy r ......1. ffull (fifo full) r .......1 rxrdy 2 w command register a (cra) w 0....... not used w .000.... no command w .001.... reset mr pointer (to mr1) w .010.... reset receiver w .011.... reset transmitter w .100.... reset error status w .101.... reset break change interrupt w .110.... start break w .111.... stop break w ....1... disable tx w .....1.. enable tx w ......1. disable rx w .......1 enable rx 2 r reserved 3 r rx holding register a 3 w tx holding register a 4 w auxiliary control register (acr) w 1....... brg set2/set1 select w .000.... counter mode, src: external (ip2) w .001.... counter mode, src: txca-1x clock of channel a transmitter w .010.... counter mode, src: txcb-1x clock of channel b transmitter w .011.... counter mode, src: crystal or external clock (x1/clk) /16 w .100.... timer mode, src: external (ip2) w .101.... timer mode, src: external (ip2) /16 w .110.... timer mode, src: crystal or external clock (x1/clk) w .111.... timer mode, src: crystal or external clock (x1/clk) /16 w ....1... delta ip3 int w .....1.. delta ip2 int w ......1. delta ip1 int w .......1 delta ip0 int 4 r input port change register (ipcr) r 1....... delta ip3 r .1...... delta ip2 r ..1..... delta ip1 r ...1.... delta ip0 r ....1... ip3 r .....1.. ip2 r ......1. ip1 r .......1 ip0 5 w interrupt mask register (imr) w 1....... input port change interrupt w .1...... delta break b interrupt w ..1..... rxrdy/ffulb interrupt w ...1.... txrdyb interrupt w ....1... counter ready interrupt w .....1.. delta break a interrupt w ......1. rxrdy/ffulla interrupt w .......1 txrdya interrupt 5 r interrupt status register (isr) r 1....... input port change r .1...... delta break b r ..1..... rxrdy/ffulb r ...1.... txrdyb r ....1... counter ready r .....1.. delta break a r ......1. rxrdy/ffulla r .......1 txrdya 6 w counter/timer upper register (ctur) 6 r counter/timer upper register (ctu) 7 w counter/timer lower register (ctlr) 7 r counter/timer lower register (ctl) 8 rw mode register b (mr1b,mr2b) 9 w clock select register b (csrb) 9 r sra status register b (srb) a w command register b (crb) a r reserved b r rx holding register b b w tx holding register b c rw interrupt vector register (ivr) d w output port configuration register (opcr) w 1....... txrdyb/opr[7] w .1...... txrdya/opr[6] w ..1..... txrdy or ffullb/opr[5] w ...1.... rxrdy or ffulla/opr[4] w ....00.. opr[3] w ....01.. counter timer output w ....10.. txcb(1x) w ....11.. rxcb(1x) w ......00 opr[2] w ......01 txca(16x) w ......10 txca(1x) w ......11 rxca(1x) d r input port register e w set output port bits command e r start counter command f w reset output port bits command f r stop counter command *end