*vga *the VGA-registers *19920301/wjvg 3c2 w: miscellaneouss output register (write only) 3cc r: miscellaneouss output register (read only) .......1 3b/3d crtc i/o address ......1. enable ram for cpu ....nn.. may only be changed if sequencer_reset_register.b1==0 ....00.. 25 Mhz clock ....01.. 28 MHz clock ....10.. external source from the feature connector ....11.. not used ...1.... disable internal video drivers (ega only) ..1..... select odd/even page, when in odd/even mode .1...... set horizontal retrace polarity low 1....... set vertical retrace polarity low 00...... not used 01...... 350 lines 10...... 400 lines 11...... 480 lines 3?a: feature control register (write only, readable at 3ca) xxxxxxxx reserved 3c2: input status register 0 (read only) ...1.... switch sense, select switch in miscellaneous output register (3c2) 1....... crt interrupt (irq2), (see also b4 of 3?5 index 11) .xx.xxxx not used 3?a: input status register 1 (read only) .......1 display active (not retracing) ....1... vertical retrace ..nn.... display setting of 2 of the attribute register output bits (select via port 3cf index 12h) xx...xx. not used 3c3: video subsystem enable register .......1 enable display xxxxxxx. not used 3c4: sequencer index register xxxxxxxx select register visible via 3c5 3c5.0: reset register .......0 asynchronous clear, (high impedance) ......0. synchronoous clear (set 0 before changing 3c2 and 3c5.01) xxxxxx.. not used 3c5.1: clocking mode register .......1 8/9 dot clocks (9 bits for mda-compatibility) .....1.. 16/8 bits shift mode (see also 3cf.5) ....1... 40/80 column mode ...1.... 32/8 bits shift mode (see also 3cf.5) ..1..... disable the display, to give the cpu more access to video memory xx....x. not used 3c5.2: map mask register .......1 enable bit plane 0 ......1. enable bit plane 1 .....1.. enable bit plane 2 ....1... enable bit plane 3 xxxx.... not used 3c5.3: character map select register ..n...nn select 8k bank 0..7 as character set if attribute bit 3 == 0 ...nnn.. select 8k bank 0..7 as character set if attribute bit 3 == 1 xx...... not used 3c5.4: memory mode register ......1. enable b14 and b15 for more than 64k memory .....1.. 16/8 bits shift mode (see also 3cf.5) ....1... 32/8 bits shift mode (see also 3cf.5) xxxx...x not used 3?4: crtc index register nnnnnnnn select register visible via 3?5 ..0..... used for chip testing on the vga, must be 0 3?5.00: horizontal total-5 3?5.01: horizontal display end-1 3?5.02: start horizontal blanking 3?5.03: end horizontal blanking ...nnnnn end horizontal blanking .nn..... delay in characters 1....... used for chip testing on the vga, must be 1 3?5.04: start horizontal retrace 3?5.05: end horizontal retrace ...nnnnn end horizontal blanking .nn..... delay in characters 1....... end horizontal blanking bit 5, (see 3?5.03) 3?5.06: vertical total (low part, see 3?5.06) 3?5.07: overflow of other registers .......n b9 of 3?5.06 ......n. b9 of 3?5.12 .....n.. b9 of 3?5.10 ....n... b9 of 3?5.09 ...n.... b9 of 3?5.18 ..n..... ba of 3?5.06 .n...... ba of 3?5.12 n....... ba of 3?5.10 3?5.08: scan line preset, for smooth scrolling in text mode ...nnnnn preset row scan .nn..... byte panning control, for 32 and 16 bit shift mode x....... not used 3?5.09: last scan line ...nnnnn last scan line ..n..... ba of 3?5.07, start vertical blank .n...... ba of 3?5.18, line compare register 1....... double every scanline in 200 line mode (200 -> 400) 3?5.0a: cursor start ...nnnnn cursor start ..1..... cursor off xx...... not used 3?5.0b: cursor end ...nnnnn cursor end .nn..... cursor skew, delay in characters x....... not used 3?5.0c: start address high 3?5.0d: start address low 3?5.0e: cursor location high 3?5.0f: cursor location low 3?5.10: vertical retrace start 3?5.11: vertical retrace end ....nnnn vertical retrace end ...0.... clear vertical interrupt (irq2) ..1..... enable vertical interrupt (irq2) at each vertical retrace .1...... 5/3 refreshes per scan 1....... protect register 0..7 3?5.12: vertical display end-1 3?5.13: logical screen width, divided by 2,4 or 8 3?5.14: underline location ...nnnnn underline location ..1..... count by 4, memory address is changed once every four clocks .1...... double word mode, b6 of 3?5.17 must be 0 x....... not used 3?5.15: start vertical blanking 3?5.16: end vertical blanking 3?5.17: mode control .......1 cga compatibility mode (a13 and a0 of memory exchanged) ......1. cga compatibility mode (a14 and a0 of memory exchanged) .....1.. divide vertical line counter by 2 ....1... divide character clock by two (to access words) ...x.... not used ..1..... put address bit 15/13 on bit 0 .1...... byte/word mode 1....... enable vertical and horizontal retrace 3?5.18: line compare 3ce: graphics 1 and 2 address register nnnnnnnn select which register is visible at 3cf 3cf.0: set/reset .......1 set/reset bit plane 0 ......1. set/reset bit plane 1 .....1.. set/reset bit plane 2 ....1... set/reset bit plane 3 3cf.1: enable set/reset .......1 enable set/reset for bit plane 0 ......1. enable set/reset for bit plane 1 .....1.. enable set/reset for bit plane 2 ....1... enable set/reset for bit plane 3 3cf.2: color compare ....nnnn color number to compare xxxx.... not used 3cf.3: data rotate .....nnn rotate n positions to the right ...00... write data without modifications ...01... AND data with latch contents ...10... OR data with latch contents ...11... XOR data with latch contents xxx..... not used 3cf.4: read map select ......nn number of bit plane to be read xxxxxx.. not used 3cf.5: mode register ......00 write mode 0: the map mask register en/disables bit planes for writing the bit mask register en/disables bits within the byte ......01 write mode 1: write contents of latch registers to memory ......10 write mode 2: the bit mask register en/disables specific pixels cpu color data is written to each pixel ......11 perform logical AND between the set/reset value and the bit mask register and write to adapter address, the enable set/reset register is ignored .....1.. test condition, puts controller output in high impedance ....0... read mode: read from bitplane selected by 3cf.5 ....1... read mode: read which pixels have same color as 3cf.2 ...1.... 16/8 bit mode (set also 3c5.4.b2) ..1..... write odd/even bits to different bit planes .1...... 256-color mode (vga-only) x....... not used 3cf.6: miscellaneous .......1 graphics/text mode ......1. write alternately to even and odd maps (set also 3cf.5.b4) after replacing b0 by b13 or b15 ....nn.. memory map ....00.. a000/128k ....01.. a000/64k ....10.. b000/32k ....11.. b800/32k xxxx.... not used 3cf.7: color don't care .......1 match bit plane 0 with specific color/always true ......1. match bit plane 1 with specific color/always true .....1.. match bit plane 2 with specific color/always true ....1... match bit plane 3 with specific color/always true xxxx.... not used 3cf.8: bit mask nnnnnnnn enable changing each specific bit not standard?: 3cf.9: processor latch 0 3cf.a: processor latch 1 3cf.b: processor latch 2 3cf.c: processor latch 3 etc.. *end